1. Field of the Invention
The present invention relates to a technology for processing a bit line contact and a storage node contact used mainly in each element of a dynamic random access memory.
2. Description of the Prior Art
FIG. 12 shows a silicon substrate 120 wherein polyplugs 125-1 and 125-2 are formed by means of a conventional process. The polyplug 125-1 secures a contact for an electrode (storage node) of a memory capacitor which stores data as a memory element of, for example, a dynamic random access memory (hereinafter referred to as DRAM) and the polyplug 125-2 secures a contact with a bit line.
As for a brief description of a process for the silicon substrate 120, first, transistors are formed on the silicon substrate 120. In the figure a gate electrode 121 is shown as a part of a transistor. Then, sidewalls 122 and an insulating interlayer film 123 are formed and two contact holes are created on both sides of the gate electrode 121 through SAC (self-aligned contact) etching. After the contact holes are created, phosphorous (P) is injected therein in an SAC manner so as to form nxe2x88x92 regions 124-1 and 124-2. Finally, polyplugs 125-1 and 125-2 are formed by depositing phosphorous (P) doped polysilicon in these contact holes.
A problem arises that, together with the miniaturization of the DRAM, the plug diameter of the contact plugs of the memory cells are scaled down so as to lower the current drive performance (Ids) of the DRAM. This is because the direct contact resistance between the polyplugs and the nxe2x88x92 regions increases.
In addition, since the nxe2x88x92 regions 124-1 and 124-2 are formed in the proximity of each other according to a conventional process, the punch through margin in the channel direction cannot be sufficiently provided. As for a more concrete description, at the time when the nxe2x88x92 regions 124-1 and 124-2 are formed in the silicon substrate by injecting phosphorous (P) in an SAC manner, the nxe2x88x92 regions diffuse in the lateral direction (channel direction) along which the gate electrode 121 exists. Therefore, the nxe2x88x92 regions are formed in the proximity of each other so as to have a risk of causing a punch through. Here xe2x80x9cpunch throughxe2x80x9d is a phenomenon where a current continues to flow between the source and the drain due to the connection between the drain depletion layer and the source depletion layer as a result of the drain depletion layer approaching too closely to the source in the transistor. Accordingly, the xe2x80x9cpunch through marginxe2x80x9d is a safety margin which prevents a punch through from occurring.
In addition, the fact that the punch through margin cannot be sufficiently provided means that the SAC injection of phosphorous (P) cannot be carried out at a higher energy level. This is because, in the case that the SAC injection is carried out at a high energy level, the diffusion of the nxe2x88x92 regions in the channel direction becomes far greater. In view of the fact that a leak, through the PN junctions between the P-well and the nxe2x88x92 regions, is reduced through SAC injection at a higher energy level, the performance of the DRAM cannot be further increased according to a conventional process.
In the case that the performance of the memory cell transistor is lowered, as described above, the margin for writing in or reading out data of a DRAM is also lowered so as to greatly influence the refresh characteristics (mainly refresh cycle time).
An object of the present invention is to reduce the direct contact resistance and to reduce a junction leak by carrying out SAC injection at a high energy level while maintaining the punch through margin.
A semiconductor integrated circuit device according to the present invention comprises a contact plug which is electrically connected to at least one of the source and the drain and which is made a conductive material including a dopant. The contact plug is formed of at least a first layer and a second layer. The first layer contacts with one of said source and drain and is made of said material including the dopant of a first concentration; said second layer is formed of a layer of said material including the dopant of a second concentration. The first concentration is higher than said second concentration. Since the first layer (high concentration phosphorous (P) doped polysilicon layer) exists on the interface with the substrate so as to contact the source and the drain, the concentration of the material of the substrate interface rises and, thereby, the direct contact resistance can be lowered.
One of said source and drain may be a region into which ions are injected with a first energy level and with a second energy level, which is higher than the first energy level, and the ions injected with said second energy level may be ions injected via said first layer. An ion injection with a high energy can be implemented for reducing the junction leak while maintaining the punch through margin in the channel direction.
A recess is formed in one of said source and drain of said substrate and the ions injected with said second energy level may be ions injected further via said recess. The ions enter into a deeper position in the substrate so that the junction leak can be reduced.